Verification Techniques for System Level Design Book
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Verification Techniques for System Level Design


  • Author : Masahiro Fujita
  • Publisher : Morgan Kaufmann
  • Release Date : 2010-07-27
  • Genre: Technology & Engineering
  • Pages : 256
  • ISBN 10 : 0080553133

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Verification Techniques for System Level Design Book Description :

This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. • First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs. • Formal verification of high-level designs (RTL or higher). • Verification techniques are discussed with associated system-level design methodology.

High Level Verification Book

High Level Verification


  • Author : Sudipta Kundu
  • Publisher : Springer Science & Business Media
  • Release Date : 2011-05-18
  • Genre: Technology & Engineering
  • Pages : 167
  • ISBN 10 : 1441993592

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High Level Verification Book Description :

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

ESL Design and Verification Book

ESL Design and Verification


  • Author : Grant Martin
  • Publisher : Elsevier
  • Release Date : 2010-07-27
  • Genre: Technology & Engineering
  • Pages : 488
  • ISBN 10 : 0080488838

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ESL Design and Verification Book Description :

Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in a

Embedded System Design Book

Embedded System Design


  • Author : Daniel D. Gajski
  • Publisher : Springer Science & Business Media
  • Release Date : 2009-08-14
  • Genre: Technology & Engineering
  • Pages : 352
  • ISBN 10 : 9781441905048

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Embedded System Design Book Description :

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail: . System modeling at different abstraction levels . Model-based system design . Hardware/Software codesign . Software and Hardware component synthesis . System verification This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.

System on a Chip Verification Book

System on a Chip Verification


  • Author : Prakash Rashinkar
  • Publisher : Springer Science & Business Media
  • Release Date : 2007-05-08
  • Genre: Technology & Engineering
  • Pages : 372
  • ISBN 10 : 9780306469954

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System on a Chip Verification Book Description :

This is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign-off. All the verification aspects in this exciting new book are illustrated with a single reference design for Bluetooth application.

EDA for IC System Design  Verification  and Testing Book

EDA for IC System Design Verification and Testing


  • Author : Louis Scheffer
  • Publisher : CRC Press
  • Release Date : 2018-10-03
  • Genre: Technology & Engineering
  • Pages : 544
  • ISBN 10 : 9781420007947

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EDA for IC System Design Verification and Testing Book Description :

Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.

Reconfigurable System Design and Verification Book

Reconfigurable System Design and Verification


  • Author : Pao-Ann Hsiung
  • Publisher : CRC Press
  • Release Date : 2018-10-08
  • Genre: Computers
  • Pages : 268
  • ISBN 10 : 9781351834926

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Reconfigurable System Design and Verification Book Description :

Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.

System Level Design with  Net Technology Book

System Level Design with Net Technology


  • Author : El Mostapha Aboulhamid
  • Publisher : CRC Press
  • Release Date : 2018-10-03
  • Genre: Computers
  • Pages : 320
  • ISBN 10 : 1439812128

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System Level Design with Net Technology Book Description :

The first book to harness the power of .NET for system design, System Level Design with .NET Technology constitutes a software-based approach to design modeling verification and simulation. World class developers, who have been at the forefront of system design for decades, explain how to tap into the power of this dynamic programming environment for more effective and efficient management of metadata—and introspection and interoperability between tools. Using readily available technology, the text details how to capture constraints and requirements at high levels and describes how to percolate them during the refinement process. Departing from proprietary environments built around System Verilog and VHDL, this cutting-edge reference includes an open source environment (ESys.NET) that readers can use to experiment with new ideas, algorithms, and design methods; and to expand the capabilities of their current tools. It also covers: Modeling and simulation—including requirements specification, IP reuse, and applications of design patterns to hardware/software systems Simulation and validation—including transaction-based models, accurate simulation at cycle and transaction levels, cosimulation and acceleration technique, as well as timing specification and validation Practical use of the ESys.NET environment Worked examples, end of chapter references, and the ESys.NET implementation test bed make this the ideal resource for system engineers and students looking to maximize their embedded system designs.

System Level Validation Book

System Level Validation


  • Author : Mingsong Chen
  • Publisher : Springer Science & Business Media
  • Release Date : 2012-09-19
  • Genre: Technology & Engineering
  • Pages : 250
  • ISBN 10 : 9781461413585

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System Level Validation Book Description :

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

Advanced Verification Techniques Book

Advanced Verification Techniques


  • Author : Leena Singh
  • Publisher : Springer Science & Business Media
  • Release Date : 2007-05-08
  • Genre: Technology & Engineering
  • Pages : 376
  • ISBN 10 : 9781402080296

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Advanced Verification Techniques Book Description :

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan

Design Methods and Applications for Distributed Embedded Systems Book

Design Methods and Applications for Distributed Embedded Systems


  • Author : Bernd Kleinjohann
  • Publisher : Springer Science & Business Media
  • Release Date : 2004-07-27
  • Genre: Computers
  • Pages : 326
  • ISBN 10 : 9781402081484

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Design Methods and Applications for Distributed Embedded Systems Book Description :

The IFIP TC-10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2004) brings together experts from industry and academia to discuss recent developments in this important and growing field in the splendid city of Toulouse, France. The ever decreasing price/performance ratio of microcontrollers makes it economically attractive to replace more and more conventional mechanical or electronic control systems within many products by embedded real-time computer systems. An embedded real-time computer system is always part of a well-specified larger system, which we call an intelligent product. Although most intelligent products start out as stand-alone units, many of them are required to interact with other systems at a later stage. At present, many industries are in the middle of this transition from stand-alone products to networked embedded systems. This transition requires reflection and architecting: The complexity of the evolving distributed artifact can only be controlled, if careful planning and principled design methods replace the - hoc engineering of the first version of many standalone embedded products.

Ingredients for Successful System Level Design Methodology Book

Ingredients for Successful System Level Design Methodology


  • Author : Hiren D. Patel
  • Publisher : Springer Science & Business Media
  • Release Date : 2008-06-06
  • Genre: Technology & Engineering
  • Pages : 208
  • ISBN 10 : 9781402084720

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Ingredients for Successful System Level Design Methodology Book Description :

ESL or “Electronic System Level” is a buzz word these days, in the electronic design automation (EDA) industry, in design houses, and in the academia. Even though numerous trade magazine articles have been written, quite a few books have been published that have attempted to de?ne ESL, it is still not clear what exactly it entails. However, what seems clear to every one is that the “Register Transfer Level” (RTL) languages are not adequate any more to be the design entry point for today’s and tomorrow’s complex electronic system design. There are multiple reasons for such thoughts. First, the c- tinued progression of the miniaturization of the silicon technology has led to the ability of putting almost a billion transistors on a single chip. Second, applications are becoming more and more complex, and integrated with c- munication, control, ubiquitous and pervasive computing, and hence the need for ever faster, ever more reliable, and more robust electronic systems is pu- ing designers towards a productivity demand that is not sustainable without a fundamental change in the design methodologies. Also, the hardware and software functionalities are getting interchangeable and ability to model and design both in the same manner is gaining importance. Given this context, we assume that any methodology that allows us to model an entire electronic system from a system perspective, rather than just hardware with discrete-event or cycle based semantics is an ESL method- ogy of some kind.

Principles of Functional Verification Book

Principles of Functional Verification


  • Author : Andreas Meyer
  • Publisher : Elsevier
  • Release Date : 2003-12-05
  • Genre: Technology & Engineering
  • Pages : 216
  • ISBN 10 : 9780080469942

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Principles of Functional Verification Book Description :

As design complexity in chips and devices continues to rise, so, too, does the demand for functional verification. Principles of Functional Verification is a hands-on, practical text that will help train professionals in the field of engineering on the methodology and approaches to verification. In practice, the architectural intent of a device is necessarily abstract. The implementation process, however, must define the detailed mechanisms to achieve the architectural goals. Based on a decade of experience, Principles of Functional Verification intends to pinpoint the issues, provide strategies to solve the issues, and present practical applications for narrowing the gap between architectural intent and implementation. The book is divided into three parts, each building upon the chapters within the previous part. Part One addresses why functional verification is necessary, its definition and goals. In Part Two, the heart of the methodology and approaches to solving verification issues are examined. Each chapter in this part ends with exercises to apply what was discussed in the chapter. Part Three looks at practical applications, discussing project planning, resource requirements, and costs. Each chapter throughout all three parts will open with Key Objectives, focal points the reader can expect to review in the chapter. * Takes a "holistic" approach to verification issues * Approach is not restricted to one language * Discussed the verification process, not just how to use the verification language

Advances in Computer Science and Engineering Book

Advances in Computer Science and Engineering


  • Author : Hamid Sarbazi-Azad
  • Publisher : Springer Science & Business Media
  • Release Date : 2008-11-23
  • Genre: Computers
  • Pages : 1017
  • ISBN 10 : 9783540899853

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Advances in Computer Science and Engineering Book Description :

It is our pleasure to welcome you to the proceedings of the 13th International C- puter Society of Iran Computer Conference (CSICC-2008). The conference has been held annually since 1995, except for 1998, when it transitioned from a year-end to first-quarter schedule. It has been moving in the direction of greater selectivity (see Fig.1) and broader international participation. Holding it in Kish Island this year represents an effort to further facilitate and encourage international contributions. We feel privileged to participate in further advancing this strong technical tradition. 60 50 40 30 20 10 0 Dec 23-26 Dec 23-25 Dec 23-25 Jan 26-28 Mar 8-10 Feb 21-23 Feb 28-30 Feb 23-26 Feb 16-19 Feb 15-18 Jan 24-26 Feb 20-22 Mar 9-11 1995 1996 1997 Iran 1999 2000 2001 U of 2002 Iran 2003 2004 2005 Iran 2006 IPM, 2007 2008 Sharif U Amirkabir U of Sharif U Shahid Isfahan, Telecom Ferdowsi Sharif U Telecom Tehran Shahid Sharif U of Tech, U of Tech, Sci/Tech, of Tech, Beheshti Isfahan Res. U, of Tech, Res. Beheshti of Tech, Tehran Tehran Tehran Tehran U, Tehran Center Mashhad Tehran Center U, Tehran Kish Island Dates, Year, Venue

Co verification of Hardware and Software for ARM SoC Design Book

Co verification of Hardware and Software for ARM SoC Design


  • Author : Jason Andrews
  • Publisher : Elsevier
  • Release Date : 2004-09-04
  • Genre: Technology & Engineering
  • Pages : 288
  • ISBN 10 : 0080476902

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Co verification of Hardware and Software for ARM SoC Design Book Description :

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools. * The only book on verification for systems-on-a-chip (SoC) on the market * Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes * Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs

Comprehensive Functional Verification Book

Comprehensive Functional Verification


  • Author : Bruce Wile
  • Publisher : Elsevier
  • Release Date : 2005-05-26
  • Genre: Computers
  • Pages : 704
  • ISBN 10 : 9780080476643

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Comprehensive Functional Verification Book Description :

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals. As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Comprehensive overview of the complete verification cycle Combines industry experience with a strong emphasis on functional verification fundamentals Includes real-world case studies

System Level Validation Book

System Level Validation


  • Author : Mingsong Chen
  • Publisher : Springer Science & Business Media
  • Release Date : 2012-09-25
  • Genre: Technology & Engineering
  • Pages : 250
  • ISBN 10 : 9781461413592

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System Level Validation Book Description :

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

Formal Verification Book

Formal Verification


  • Author : Erik Seligman
  • Publisher : Morgan Kaufmann
  • Release Date : 2015-07-24
  • Genre: Computers
  • Pages : 408
  • ISBN 10 : 9780128008157

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Formal Verification Book Description :

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulation Understand formal verification tools and how they differ from simulation tools Create instant test benches to gain insight into how models work and find initial bugs Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Book

Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems


  • Author : S. Ramesh
  • Publisher : Springer Science & Business Media
  • Release Date : 2007-08-26
  • Genre: Technology & Engineering
  • Pages : 300
  • ISBN 10 : 9781402062544

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Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Book Description :

This volume is the proceedings of a workshop organized by General Motors research and development laboratory in Bangalore, India. It was the first of its kind to be run by an automotive major to bring together the leaders in the field of embedded systems development to present state-of-the-art work, and to discuss future strategies for addressing the increasing complexity of embedded control systems. The workshop consisted of invited talks given by leading experts and researchers from academic and industrial organizations. It covered all areas of embedded systems development.

A Framework for Automated HW SW Co Verification of SystemC Designs Using Timed Automata Book

A Framework for Automated HW SW Co Verification of SystemC Designs Using Timed Automata


  • Author : Paula Herber
  • Publisher : Logos Verlag Berlin GmbH
  • Release Date : 2010
  • Genre: Computers
  • Pages : 145
  • ISBN 10 : 9783832525118

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A Framework for Automated HW SW Co Verification of SystemC Designs Using Timed Automata Book Description :

In this dissertation, we present a systematic, comprehensive, and formally founded quality assurance process, which allows automated co-verification of digital hardware/software systems that are modeled in SystemC. The main idea is to apply model checking to verify that an abstract design meets a requirements specification and to generate conformance tests to check whether refined designs conform to this abstract design. As formal foundation, we define a formal semantics of SystemC by a transformation into the well-defined semantics of UPPAAL timed automata. The automatically generated timed automata model can be verified using the UPPAAL model checker and it can be used to generate conformance tests. With that, we obtain guarantees about liveness, safety, and timing properties of the abstract design, which serves as a specification, and we can ensure the consistency of each refined design to that. The result is a HW/SW co-verification flow that supports the HW/SW co-development process continuously from abstract design down to the implementation. The complete verification flow is implemented in our Framework for the Verification of SystemC designs using Timed Automata (VeriSTA) and its applicability and performance are shown by experimental results.